* Memory Cell : Dynamic memory( DRAM )
* Refresh: Completely free
* Power Down: Control by CS2( No Data Retention )
* Byte Control : Capable of single byt.
PRELIMINARY (December, 2003, Version 0.0)
1
AMIC Technology Corp.
A64S16161
Block Diagram
A0 A1 A2 A3 A4 A5 A6 Row.
Pin Name CS1# CS2 WE# OE# A0 to A20 IO0-7 IO8-15 LB# UB# VCC VSS Description Chip select 1 ( Low Active ) Chip select 2 ( High Active ) Write enable ( Low Active ) Output enable ( Low Active ) Address Input ( A0 to A2 : Page Address) Lower Byte Input.
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